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RM0008
12.5.7
Digital-to-analog converter (DAC)
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC2DHR[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved.
Bits 15:4 DACC2DHR[11:0] : DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved.
12.5.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC2DHR[7:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:8 Reserved.
Bits 7:0 DACC2DHR[7:0] : DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.
12.5.9
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DACC2DHR[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC1DHR[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved.
Bits 27:16 DACC2DHR[11:0] : DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Doc ID 13902 Rev 9
249/995
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